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Insider Brief
- Altera and Riverlane announced a partnership to support quantum hardware developers with FPGA-based systems for parallel quantum control and real-time error correction.
- Riverlane validated its QEC Interface (QECi) design example on an Altera Agilex 7 FPGA, with the design example available through its open-source GitHub repository.
- The partnership combines QECi’s standardized interface with Agilex FPGA processing and high-speed connectivity to support low-latency data exchange between quantum control and error-correction systems.
PRESS RELEASE — Altera , the world’s largest pure-play FPGA solutions provider, and Riverlane , the world leader in quantum error correction (QEC) technology and tools, today announced their partnership to help quantum hardware developers build more flexible control and error-correction systems that can process quantum data in parallel and rapidly move correction information through the control stack with predictable timing using Altera FPGAs. Riverlane has also joined the Altera Solutions Acceleration Partner Program (ASAP), expanding the ecosystem of specialized solutions that help customers reduce integration complexity and bring FPGA-based systems to market faster.
Through the partnership, Riverlane has validated its QEC Interface (QECi) design example on an Altera Agilex 7 FPGA. The device’s high-speed transceivers enable the fast, low-latency data movement required between quantum control and error-correction systems. Riverlane has published the design example in its open-source QECi repository on GitHub, giving developers a starting point for evaluating QEC data movement and integration with Agilex FPGA-based quantum control systems.
“Quantum error correction requires tremendous parallel processing, high-speed connectivity and predictable timing as systems scale,” said Farhad Shafai, vice president of business solutions at Altera . “ Riverlane ’s validation of its low-latency QECi protocol on Agilex 7 and Agilex 9 FPGAs demonstrates how our programmable platforms can efficiently connect quantum control and error-correction technologies.”
QECi standardizes how error-correction data is exchanged between quantum control systems and QEC hardware, enabling developers to integrate different technologies as quantum architectures evolve. Running QECi on Agilex FPGAs provides the high-speed connectivity, deterministic low latency, and programmable processing needed for real-time quantum error correction.
“ Riverlane is focused on making quantum error correction practical across the full quantum-computing ecosystem,” said Marco Ghibaudi, vice president of engineering at Riverlane. “Validating the QECi design example on Altera Agilex hardware demonstrates how an open interface can help connect quantum control systems with real-time error-correction technology and gives developers an accessible way to begin evaluating the integration.”
Altera Agilex 7 FPGAs and SoCs provide programmable fabric, high-speed transceivers, dense I/O, and 2x better performance per watt (vs. competing 7nm FPGAs) for demanding control and data-processing workloads. These capabilities can help quantum-system developers implement parallel processing and high-bandwidth connectivity for qubit control, readout, and QEC data paths. Across the broader Agilex portfolio, Altera’s F-Tile high-speed transceivers are offered in both Agilex 7 FPGAs and Agilex 9 Direct RF FPGAs with integrated data converters, featuring up to 64 Gsps of sample rate and 36 GHz of RF range.
Riverlane experts will be available at the Riverlane booth at IEEE Quantum Week 2026 [booth 309], taking place September 13–18 in Toronto, Canada, to discuss the QECi solution on Agilex FPGAs and its role in advancing quantum error correction.
Developers can access the Riverlane QECi design example for Altera devices on GitHub . Learn more about Altera’s quantum-computing solutions at altera.com .