Insider Brief
- izmo Microsystems and IIT Madras have entered Phase II of the Centre for Programmable Photonic Integrated Circuits and Systems (CPPICS), a five-year silicon photonics program with a total outlay of ₹99.94 crore.
- The SPECTRA program will target silicon photonics applications in data-center transceivers, microwave photonics, quantum technologies and photonic computing for AI.
- izmo Microsystems will contribute packaging, testing and integration expertise, including work on co-packaged optics and a 1.6 Tbps silicon photonics transceiver engine.
PRESS RELEASE — izmo Limited (NSE: IZMO) (BSE: 532341) today announced that its semiconductor subsidiary, izmo Microsystems Pvt. Ltd., has entered into a Memorandum of Understanding with the Indian Institute of Technology Madras (IIT Madras) for Phase II of the Centre for Programmable Photonic Integrated Circuits and Systems (CPPICS).
The Phase II program, titled Silicon Photonics Enabled Cutting-edge Technology Research and Applications (SPECTRA) , has been sanctioned by the Ministry of Electronics and Information Technology (MeitY), Government of India, with a total project outlay of ₹99.94 crore. The five-year program includes a MeitY contribution of ₹97.54 crore and a ₹2.40 crore cash and in-kind commitment from izmo Microsystems.
CPPICS Phase II is designed to advance silicon photonics technologies from research towards commercially deployable products, covering photonic integrated circuit design, fabrication, characterization, advanced packaging, testing and system integration.
Silicon Photonics for the AI infrastructure era
The program comes at a time when optical connectivity is becoming critical infrastructure for AI and high-performance computing.
As GPU and accelerator clusters scale, data-center networks require substantially higher bandwidth while controlling power consumption, latency and interconnect density. This is driving the transition towards 800G and 1.6T optical interconnects, silicon photonics and, increasingly, co-packaged optics (CPO).
According to LightCounting , global sales of optical transceivers and related products reached $26.8 billion in 2025, up 74% year-on-year. The research firm estimates the optical transceiver market at approximately $40 billion in 2026 , with silicon-photonics-based transceivers expected to represent more than half of the market for the first time.
LightCounting further estimates that the market for optical chips used across transceivers, active optical cables and near- and co-packaged optics could grow from approximately $4 billion in 2025 to $15 billion by 2031.
The transition is already moving into commercial infrastructure, with major networking and semiconductor companies introducing silicon-photonics-based co-packaged-optics platforms for large AI clusters.
Targeting 1.6 Tbps Optical Engines and Co-Packaged Optics
CPPICS Phase II targets commercially viable photonic technologies across four major application areas: high-speed optical transceivers for data centers, microwave photonics for advanced wireless communications, quantum photonics, and photonic computing for AI.
Among the planned developments is a 1.6 Tbps silicon photonics transceiver engine operating at 1550 nm for high-performance computing and data-center routing. The project also targets microwave photonic engines operating beyond 50 GHz, integrated QRNG/QKD systems and photonic processors for AI workloads.
The program also proposes development of a silicon photonics Process Design Kit incorporating more than 100 IP blocks for 200 mm wafer platforms, supporting the design and manufacture of increasingly complex photonic integrated circuits.
izmo Microsystems to Drive Packaging and Industrialization
A key challenge in silicon photonics is converting a fabricated photonic chip into a reliable and manufacturable optical system.
CPPICS Phase II specifically envisages development of a volume photonics packaging ecosystem in collaboration with izmo Microsystems, addressing precision assembly, photonic packaging, testing and reliability required for commercial deployment.
Under the program, izmo Microsystems’ role progresses from packaging architecture and CPO interface definition to PIC-EIC co-integration, fiber alignment and attachment, production-grade packaging, process optimization, prototype assembly and reliability validation.
The five-year roadmap ultimately targets a certified co-packaged optics design rule and service capability, creating a pathway from silicon photonics research and foundry fabrication through packaging, qualification and system-level deployment.
Dinanath Soni, Director, izmo Microsystems Pvt. Ltd., said:
“Silicon photonics is becoming a critical technology for the next generation of AI and data-center infrastructure as network speeds move from 400G and 800G towards 1.6T and beyond.
The challenge is no longer only designing the photonic chip. Converting that chip into a reliable product requires precision packaging, fiber attachment, electronic-photonic integration, thermal management and high-speed testing.
CPPICS Phase II brings together IIT Madras’ silicon photonics research capabilities with izmo Microsystems’ advanced packaging and manufacturing expertise. Our role is to help move these technologies from research prototypes towards production-ready modules and co-packaged optical systems.”
Building on CPPICS Phase I
CPPICS Phase II builds on the first phase of the program, which achieved more than 95% of its planned milestones and generated research, IP and prototypes across programmable photonics, microwave photonics and quantum technologies.
Phase II expands the program toward technology translation, industrialization and commercialization, with applications spanning data centers, telecommunications, defence, quantum technologies and advanced computing.
Through the collaboration, izmo Microsystems intends to strengthen its advanced photonic packaging capabilities and participate in the emerging global market for silicon photonics, high-speed optical interconnects and co-packaged optics for AI and high-performance computing infrastructure.