Quantum Networkpowered by
searchSubscribe
Quantum Network

News, research, careers and the quantum industry, in one place.

  • alternate_email
  • search

Explore

  • Editorial
  • Research Hub
  • Events
  • Opportunities
  • About Us

Community

  • Join the Community
  • Learning Resources
  • Contact Us

Contact

A-307, Kailash Business Park,
Vikhroli (W), Mumbai – 400079

022 49646504

[email protected]

  • Newsletter
  • India Quantum Pulse
Quantum Networkpowered by
searchSubscribe
Universal Quantum Details Iterative Redecode Scheme for Fast Transversal Fault-Tolerant Logic
RESEARCH·Nov 3, 2026·1 MIN READ

Universal Quantum Details Iterative Redecode Scheme for Fast Transversal Fault-Tolerant Logic

Universal Quantum's new Iterative Redecode Scheme (IRS) addresses the error-correlation bottleneck in fast transversal quantum logic. This decoding architecture, detailed in a paper by Mark Webber and colleagues, uses a propagation-assisted local (PAL) framework to coordinate corrections across logical blocks, resulting in significantly lower logical error rates compared to other decoders. The IRS achieves this by alternating local Minimum-Weight Perfect Matching (MWPM) with deterministic Pau...

Source

Quantum Computing Report

Author: Mohamed Abdel-Kareem

Published Nov 3, 2026

Summarised/rewritten with AI from Quantum Computing Report

Read original articlearrow_forward

Universal Quantum's new Iterative Redecode Scheme (IRS) addresses the error-correlation bottleneck in fast transversal quantum logic. This decoding architecture, detailed in a paper by Mark Webber and colleagues, uses a propagation-assisted local (PAL) framework to coordinate corrections across logical blocks, resulting in significantly lower logical error rates compared to other decoders. The IRS achieves this by alternating local Minimum-Weight Perfect Matching (MWPM) with deterministic Pauli-frame propagation, allowing for efficient and accurate error correction in fault-tolerant quantum hardware.

The post Universal Quantum Details Iterative Redecode Scheme for Fast Transversal Fault-Tolerant Logic appeared first on Quantum Computing Report .

UNCATEGORIZEDERROR-CORRECTIONRESEARCH

Report a problem / takedown

ABOUT THIS STORY

Source
Quantum Computing Report
Published
Nov 3, 2026
Category
RESEARCH
Read original articlearrow_forward

More from Quantum Network

Alice & Bob Demonstrates Multi-Hour Physical Bit-Flip Suppression on Single-Cat and Helium 2 Processors
RESEARCH

Alice & Bob Demonstrates Multi-Hour Physical Bit-Flip Suppression on Single-Cat and Helium 2 Processors

Alice & Bob has achieved a significant breakthrough in quantum computing, demonstrating macroscopic bit-flip lifetimes exceeding one hour on their bosonic cat-qubit hardware. Their single-qubit device showed an average idle bit-flip lifetime of 44 minutes, while their 12-qubit Helium 2 processor achieved lifetimes of over three to four hours. This advancement provides crucial experimental validation for their fault-tolerant quantum computing architecture and brings them closer to realizi...

Nov 2, 2026

arrow_forward
Sandia and Quantinuum Introduce Logical Gate Set Tomography to Map Fault-Tolerant Qubit Noise
RESEARCH

Sandia and Quantinuum Introduce Logical Gate Set Tomography to Map Fault-Tolerant Qubit Noise

Researchers from Sandia National Laboratories and Quantinuum have introduced "Logical GST," a protocol that provides the first self-consistent, full tomographic reconstruction of a universal single-qubit logical gate set. This was implemented on a single logical qubit encoded in the [[7, 1, 3]] Steane code on the Quantinuum System Model H1-1. The study confirmed the assumption that quantum error correction converts complex physical noise into simple, uncorrelated Pauli-stochastic channels, bu...

Oct 31, 2026

arrow_forward
Quantinuum Chief Scientist Argues Physical Fidelity Trumps Gate Speed in Fault-Tolerant Scaling Race
RESEARCH

Quantinuum Chief Scientist Argues Physical Fidelity Trumps Gate Speed in Fault-Tolerant Scaling Race

Quantinuum's Chief Scientist, Harry Buhrman, argues that high physical fidelity in quantum gates is more critical than raw gate speed for achieving fault-tolerant quantum computing. He highlights Quantinuum's trapped-ion architecture as superior to superconducting platforms due to its low error rates, which significantly reduce the resources needed for quantum error correction. While trapped-ion systems currently have slower gate speeds, Quantinuum aims to overcome this limitation by 2029 to...

Oct 31, 2026

arrow_forward
RESEARCH

Alice & Bob Demonstrates End-to-End Shor’s Algorithm Compilation Requiring 23,000 Cat Qubits to Break RSA-2048

Alice & Bob, in collaboration with other researchers, have demonstrated that Shor's algorithm could factor an RSA-2048 integer using 22,593 physical cat qubits in 3.14 days. This reduces the physical qubit footprint by roughly a factor of 40 compared to previous estimates. The research highlights the accelerated convergence of algorithmic efficiency and bosonic error correction, reinforcing the need for critical infrastructure to migrate to post-quantum standards by 2035. The post Alice...

Oct 30, 2026

arrow_forward
Quantum Network

News, research, careers and the quantum industry, in one place.

  • alternate_email
  • search

Explore

  • Editorial
  • Research Hub
  • Events
  • Opportunities
  • About Us

Community

  • Join the Community
  • Learning Resources
  • Contact Us

Contact

A-307, Kailash Business Park,
Vikhroli (W), Mumbai – 400079

022 49646504

[email protected]

  • Newsletter
  • India Quantum Pulse