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Insider Brief
- QC Design has integrated its Plaquette design-automation platform with NVIDIA CUDA-Q Logical to enable hardware-realistic simulations of lattice surgery and other fault-tolerant quantum protocols.
- The integration combines CUDA-Q Logical’s logical workload and QEC architecture layer with Plaquette’s device-specific noise models to assess logical protocols under physical hardware errors.
- In an initial simulation, QC Design found that a 0.2% leakage rate on two-qubit gates reduced the circuit-noise threshold by approximately 60% for a lattice-surgery CX gate between surface-code logical qubits.
PRESS RELEASE — QC Design today announced an integration between Plaquette, its design-automation platform for fault-tolerant quantum computing (FTQC), and NVIDIA CUDA-Q Logical, the open, extensible logical layer of the CUDA-Q platform. This collaboration enables quantum hardware teams to perform accurate simulations of lattice surgery and other logical protocols using realistic, physics-based hardware error models.
CUDA-Q Logical lets developers express high-level quantum programs in terms of fault-tolerant operations, evaluate them across different quantum error correction (QEC) codes and system architectures using consistent workload definitions and metrics, and understand the resources required to run them. Plaquette applies device-specific noise models to compiled logical protocols and simulates how physical imperfections propagate through lattice surgery and other fault-tolerant operations. The integration connects logical compilation and physical-level simulation in a unified design workflow.
This integration addresses a key challenge that hardware teams have struggled with so far: the tools that compile logical algorithms and those that model real device physics have been developed independently based on different underlying assumptions, so logical performance has been estimated from idealized assumptions and Pauli noise models. With this new integration, logical algorithms can now be assessed under realistic conditions, providing reliable insight for the development of quantum architectures. For the quantum computing ecosystem, this integration thus provides realistic resource estimates across all hardware platforms. As a result FTQC roadmaps can now be built on a solid-foundation of data-backed resource estimates.
In an initial demonstration, QC Design used the integration to study a lattice-surgery CX gate between two surface-code logical qubits under non-Pauli noise. In the simulated hardware model, a 0.2% leakage rate on two-qubit entangling gates reduced the circuit-noise threshold by approximately 60%. The result illustrates how even low leakage rates can materially alter conclusions about viable fault-tolerant architectures.
“Fault-tolerant architectures ultimately have to work on real hardware, where leakage, coherent errors and shuttling errors can materially change logical performance,” said Dr. Ish Dhand, co-founder and CEO of QC Design . “By connecting Plaquette’s hardware-realistic models with CUDA-Q Logical, teams can test those effects earlier and make architecture decisions using assumptions that reflect their own devices.”
“Quantum computing developers need an open, extensible way to express fault-tolerant workloads and evaluate them across quantum error correction codes and system architectures,” said Sam Stanwyck, Director, Quantum Product at NVIDIA . “With CUDA-Q Logical, developers can easily explore all elements of fault tolerant applications, with Plaquette error accounting allowing additional resource estimation capabilities.”
The integration brings fault-tolerant quantum computing closer to the kind of integrated design workflow already standard in other complex engineering disciplines such as semiconductors. By connecting CUDA-Q Logical’s logical workload and architecture layer with Plaquette’s hardware-realistic simulation capabilities, teams can evaluate how choices made at one layer affect performance at the other. This gives quantum hardware developers a more direct path from logical algorithm requirements to the architecture decisions needed to build systems that can meet them.